The present disclosure relates to the processing of substrates. In particular, it provides methods utilized to suppress damage to process layers.
As critical dimensions of features formed on substrates continue to shrink, the use of low dielectric constant (Low-k) materials (materials having a dielectric constant that is smaller than silicon dioxide) in substrate processing has become more important. Low-k materials may be used to form low-k layers that are utilized in a wide variety of points of a substrate process flow, including front end of line (FEOL) and back end of line (BEOL) process steps. For example, it has been found that the lower dielectric constant of low-k dielectric layers improves electrical characteristics (for example capacitance characteristics) which improve device performance when a BEOL conductor line is embedded within a dielectric layer.
The shrinking of critical dimensions has also placed increased demands upon the alignment and overlay of the various patterned layers of a substrate with respect to each other. To address such needs at BEOL conductor and via layers, fully self-aligned via (FSAV) processes have been proposed for the connection of an upper and lower conductor layer (typically metal layers) through a via. Various techniques have been utilized to form a FSAV. In many embodiments, a FSAV may utilize a process in which a recess is formed in the lower conductor layer. The formation of a conductor recess is typically accomplished through the use of a wet etch or dry plasma etch. A dry plasma etch may be preferred for costs benefits.
It has been found, however, that when a FSAV process is utilized with low-k dielectrics, the use of a plasma etch to provide the conductor recess may damage the low-k dielectric layer. For example, the plasma etch may damage the low-k dielectric material by increasing the dielectric constant at the surface of the low-k dielectric layer, thus hindering the benefit of using a low-k material. FIGS. 1A-1C illustrate the impact of the use of a plasma etch to form a metal recess in a low-k dielectric layer. As shown in FIG. 1, a structure 100 is provided on a substrate 105. A low-k layer 115 (for example a low-k dielectric layer) is provided along with an underlying layer 110. Conductor layer 120 may be formed as shown. A barrier or liner layer 125 may be provided under the conductor layer 120 between the conductor layer 120 and the low-k layer 115.
The structure 100 may then be exposed to a plasma 130 as shown in FIG. 1B in order to provide recesses in the conductor layer 120 as part of the FSAV process. The plasma etch recess process may lead to a damaged low-k layer 135 at the surface of the low-k dielectric layer as shown in FIG. 1C. The dielectric constant of the damaged low-k layer 135 may be increased due to damage caused by the recess plasma etch. The damaged low-k layer 135 may thus have a higher dielectric constant than undamaged portions of the low-k layer 115. The regions of a higher dielectric constant may negate some of the benefits of utilizing the low-k material, for example impacting electrical device characteristics.
Thus, it would be desirable to utilize a process flow in which low-k layers are not damaged due to conductor recess etching process steps.